module Writeback (

	input       [0:0]   clock,

	// Memory
	input       [4:0]   mem_wb_regdest,
	input	    [0:0]   mem_wb_writereg,
	input	   [31:0]	mem_wb_wbvalue,

	// Registers
	output reg	[0:0]   wb_reg_en,
	output reg	[4:0]	wb_reg_addr,
	output reg [31:0]   wb_reg_data,

	// Forwarding
	output	   [31:0]   wb_fw_wbvalue,
	output	    [0:0]   wb_fw_writereg

    );

	reg        [31:0]   value;
	reg         [0:0]   signal;

	assign wb_fw_wbvalue = value;
	assign wb_fw_writereg = signal;

	always @(negedge(clock)) begin

		value = mem_wb_wbvalue;
		signal = mem_wb_writereg;

		wb_reg_en = mem_wb_writereg;
		wb_reg_addr = mem_wb_regdest;
		wb_reg_data = mem_wb_wbvalue;

	end

endmodule
